Defense Notices

This project is not a new idea or an innovative method, this project consists in the implementation of techniques already used in the consumer industry.

The purpose of this project is to implement a compact and low-weight Maximum Power Point Tracking (MPPT) Solar Harvesting Device intended for a small fixed-wing unmanned aircraft. For the aircraft selected, the load could be subsidized up to 25% by the MPPT device and installed solar cells.

The MPPT device was designed around the Texas Instruments SM72445 Integrated Circuit and its technical documentation. The prototype was evaluated using a Photovoltaic Profile Emulator Power Supply and a LiPo battery.

The device performed MPPT in one of the different tested current-voltage (IV) profiles reaching Maximum Power Point (MPP).  The device did not maintain the MPP. Under an additional external DC load or different IV profiles, the emulator operates in prohibited operating conditions. The probable cause of the failed behavior is due to instability in the emulator’s output. The inputs to the controller and response behaviors of the H-bridge circuit were as expected and designed.

The main aim of the thesis is to identify provisions employed by the compiler to ensure the security of any arbitrary binary. These provisions are security techniques applied automatically by the compiler during the system build process. Compilers provide a number of security checks, that can be applied statically or at compile time, to protect the software from attacks that target code vulnerabilities. Most compilers use warnings to indicate potential code bugs and run-time security checks which add instrumentation code in the binary to detect problems during execution. Our first work is to develop a language-agnostic and compiler-agnostic experimental framework which determines the presence of targeted compiler-based run-time security checks in any binary. Our next work is focused on exploring if unresolved compiler generated warnings can be detected in the binary when the source code is not available.

Metagenomics is the study of microbial genomes from one common environment and in most cases, metagenomic data refer to the whole-genome shotgun sequencing data of the microbiota, which are fragmented DNA sequences from all regions in the microbial genomes. Because the data are generated without laboratory culture, they provide a more unbiased insight to and uniquely enriched information of the microbial community. Currently many researchers are interested in metagenomic data, and a sea of software exist for various purposes at different analyzing stages. Most researchers build their own analyzing pipeline on their expertise, and the pipelines for the same purpose built by two researchers might be disparate, thus affecting the conclusion of experiment. 

My research interests involve: (1) We first developed an assembly graph-based ncRNA searching tools, named DRAGoM, to improve the searching quality in metagenomic data. (2) We proposed an automatic metagenomic data analyzing pipeline generation system to extract, organize and exploit the enormous amount of knowledge available in literature. The system consists of two work procedures: construction and generation. In the construction procedure, the system takes a corpus of raw textual data, and updates the constructed pipeline network, whereas in the genera- tion stage, the system recommends analyzing pipeline based on the user input. (3) We performed a meta-analysis on the taxonomic and functional features of the gut microbiome from non-small cell lung cancer patients treated with immunotherapy, to establish a model to predict if a patient will benefit from immunotherapy. We systematically studied the taxonomical characteristics of the dataset and used both random forest and multilayer perceptron neural network models to predict the patients with progressing-free survival above 6 months versus those below 3 months.

The complexity of the design and fabrication process of electronic devices is advancing with their ability to provide wide-ranging functionalities including data processing, sensing, communication, artificial intelligence, and security. Due to these complexities in the design and manufacturing process and associated time and cost, system developers often prefer to procure off-the-shelf components directly from the market instead of developing custom Integrated Circuits (ICs) from scratch. Procurement of Commerical-Off-The-Shelf (COTS) components reduces system development time and cost significantly, enables easy integration of new technologies, and facilitates smaller production runs. Moreover, since various companies use the same COTS IC, they are generally available in the market for a long period and are easy to replace. 

Although utilizing COTS parts can provide many benefits, it also introduces serious security concerns. None of the entities in the COTS IC supply chain are trusted from a consumer's perspective, leading to a ”Zero Trust” supply chain threat model. Any of these entities could introduce hidden malicious circuits or hardware Trojans within the component that could help an attacker in the field extract secret information (e.g., cryptographic keys) or cause a functional failure. Existing solutions to counter hardware Trojans are inapplicable in a zero trust scenario as they assume either the design house or the foundry to be trusted. Moreover, many solutions require access to the design for analysis or modification to enable the countermeasure. 

In this work, we have proposed a software-oriented countermeasure to ensure the confidentiality of secret assets against hardware Trojan attacks in untrusted COTS microprocessors. The proposed solution does not require any supply chain entity to be trusted and does not require analysis or modification of the IC design.  

To protect secret assets in an untrusted microprocessor, the proposed method leverages the concept of residue number coding to transform the software functions operating on the asset to be homomorphic. We have presented a detailed security analysis to evaluate the confidentiality of a secret asset under Trojan attacks using the secret key of the Advanced Encryption Standard (AES) program as a case study. Finally, to help streamline the application of this protection scheme, we have developed a plugin for the LLVM compiler toolchain that integrates the solution without requiring extensive source code alterations.

While identifying an object in an image is almost an instantaneous task for the human visual perception system, it takes more effort and time to process and identify a camouflaged object - an entity that flawlessly blends with the background in the image. This explains why it is much more challenging to enable a machine learning model to do the same, in comparison to generic object detection or salient object detection.

This project implements a framework called Search Identification Network, that simulates the search and identification pattern adopted by predators in hunting their prey and applies it to detect camouflaged objects. The efficiency of this framework in detecting polyps in medical image datasets is also measured.

Matched processing is fundamental filtering operation within radar signal processing to estimate scattering in the radar scene based on the transmit signal. Although matched processing maximizes the signal-to-noise ratio (SNR), the filtering operation is ineffective when interference is captured in the receive measurement. Adaptive interference mitigation combined with matched processing has proven to mitigate interference and estimate the radar scene. But, a known caveat of matched processing is the resulting sidelobes that may mask other scatterers. The sidelobes can be efficiently addressed by windowing but this approach also comes with limited suppression capabilities, loss in resolution, and loss in SNR. The recent emergence of mismatch processing has shown to optimally reduce sidelobes while maintaining nominal resolution and signal estimation performance. Throughout this work, re-iterative minimum-mean square error (RMMSE) adaptive and least-squares (LS) optimal mismatch processing are proposed for enhanced signal estimation in unison with adaptive interference mitigation for various radar applications including random pulse repetition interval (PRI) staggering pulse-Doppler radar, airborne ground moving target indication, and radar & communication spectrum sharing. Mismatch processing and adaptive interference cancellation each can be computationally complex for practical implementation. Sub-optimal RMMSE and LS approaches are also introduced to address computational limitations. The efficacy of these algorithms are presented using various high-fidelity Monte Carlo simulations and open-air experimental datasets. 

Quantum computing is a promising technology that can potentially demonstrate supremacy over classical computing in solving specific problems. At present, two critical challenges for quantum computing are quantum state decoherence, and low scalability of current quantum devices. Decoherence places constraints on realistic applicability of quantum algorithms as real-life applications usually require complex equivalent quantum circuits to be realized. For example, encoding classical data on quantum computers for solving I/O and data-intensive applications generally requires quantum circuits that violate decoherence constraints. In addition, current quantum devices are of small-scale having low quantum bit(qubit) counts, and often producing inaccurate or noisy measurements, which also impacts the realistic applicability of real-world quantum algorithms. Consequently, benchmarking of existing quantum algorithms and investigation of new applications are heavily dependent on classical simulations that use costly, resource-intensive computing platforms. Hardware-based emulation has been alternatively proposed as a more cost-effective and power-efficient approach. This work proposes a hardware-based emulation methodology for quantum algorithms, using cost-effective Field-Programmable Gate-Array(FPGA) technology. The proposed methodology consists of three components that are required for complete emulation of quantum algorithms; the first component models classical-to-quantum(C2Q) data encoding, the second emulates the behavior of quantum algorithms, and the third models the process of measuring the quantum state and extracting classical information, i.e., quantum-to-classical(Q2C) data decoding. The proposed emulation methodology is used to investigate and optimize methods for C2Q/Q2C data encoding/decoding, as well as several important quantum algorithms such as Quantum Fourier Transform(QFT), Quantum Haar Transform(QHT), and Quantum Grover’s Search(QGS). This work delivers contributions in terms of reducing complexities of quantum circuits, extending and optimizing quantum algorithms, and developing new quantum applications. For higher emulation performance and scalability of the framework, hardware design techniques and hardware architectural optimizations are investigated and proposed. The emulation architectures are designed and implemented on a high-performance-reconfigurable-computer(HPRC), and proposed quantum circuits are implemented on a state-of-the-art quantum processor. Experimental results show that the proposed hardware architectures enable emulation of quantum algorithms with higher scalability, higher accuracy, and higher throughput, compared to existing hardware-based emulators. As a case study, quantum image processing using multi-spectral images is considered for the experimental evaluations. 

Multi-core, integrated CPU-GPU embedded systems provide new capabilities for sophisticated real-time systems with size, weight, and power limitations; however, interference between shared resources remains a challenge in providing necessary performance guarantees. The shared main memory is a notable system bottleneck - causing throughput slowdowns and timing unpredictability.

In this paper, we propose a full system mechanism which can provide memory bandwidth regulation across both CPU and the GPU complexes. This system monitors the memory controller accesses directly through hardware statistics counters, performs memory regulation at the software level for real-time CPU tasks, and incorporates a feedback-based throttling mechanism for non-critical GPU kernels using hardware within the NVIDIA Tegra X1 memory controller subsystem. The system is built as a loadable Linux kernel module that extends the MemGuard tool. We show that this system can make CPU task execution more predictable against co-running, memory intensive interference on either CPU or GPU.

Remote attestation is a technology for establishing trust in a remote computing system.  Core to the integrity of the attestation mechanisms themselves are components that orchestrate, cryptographically bundle, and appraise measurements of the target system.  Copland is a domain-specific language for specifying attestation protocols that operate in diverse, layered measurement topologies.  In this work we formally define and verify the Copland Compiler and Copland Virtual Machine for executing Copland protocols to produce evidence.  Appraisal is a dual un-bundling procedure over the raw evidence segments produced by arbitrary Copland-based attestations.  All artifacts are implemented as monadic, functional programs in the Coq proof assistant and verified with respect to a Copland reference semantics that characterizes attestation-relevant event traces and cryptographic evidence shapes.  Appraisal soundness is positioned within a novel end-to-end workflow that leverages formal properties of the attestation components to discharge assumptions about honest Copland participants.  These assumptions inform an existing model-finder tool that analyzes a Copland scenario in the context of an active adversary attempting to subvert attestation.  An initial case study exercises this workflow through the iterative design and analysis of a Copland protocol and accompanying security architecture for an Unmanned Air Vehicle DARPA demonstration platform.  We conclude by instantiating a more diverse benchmark of attestation patterns called the “Flexible Mechanisms for Remote Attestation”, leveraging Coq's built-in code synthesis to integrate the formal artifacts within an executable attestation environment.

Multimedia networking is the area of study associated with the delivery of heterogeneous data including, but not limited to, imagery, video, audio, and interactive content. Multimedia and communication network researchers have continually struggled to devise solutions for addressing the three core challenges in multimedia delivery: security, reliability, and performance. Solutions to these challenges typically exist in a spectrum of compromises achieving gains in one aspect at the cost of one or more of the others. Networked videogames represent the pinnacle of multimedia challenges presented in a real-time, delay-sensitive, interactive format. Continual improvements to multimedia delivery have led to tools such as buffering, redundant coupling of low-resolution alternative data streams, congestion avoidance, and forced in-order delivery of best-effort service; however, videogames cannot afford to pay the latency tax of these solutions in their current state.



Practical assessments of contemporary videogame networking applications have confirmed security and performance flaws existing in well-funded, top-tier videogame titles.  This dissertation addresses these challenges through the application of a novel networking protocol, leveraging emerging blockchain technology to provide security, reliability, and performance gains to distributed network applications. This work provides a comprehensive overview of contemporary networking approaches used in delivering videogame multimedia content and their associated shortcomings. Additionally, key elements of blockchain technology are identified as focal points for solution development, notably the application of distributed ledger technology, consensus mechanisms, and smart contracts.  We conducted empirical evaluations of a network video game using both traditional TCP and UDP sockets compared with a modified video game sending state updates via hyperledger fabric channels. Reliability and security were substantially improved with no significant impact on performance.



The broader impact of this research is the improvement of real-time delivery for interactive multimedia content. This has wide-reaching effects across multiple industries including entertainment streaming, virtual conferencing, video games, manufacturing, financial transactions, and autonomous systems.