Memory QoS Mechanisms for Predictable and Performant Real-Time Systems

Commercial-off-the-shelf (COTS) multicore processors are increasingly used in safety-critical real-time systems due to their higher performance and improved size, weight, and power (SWaP) characteristics. However, modern platforms are designed for average-case performance, which works in direct opposition to the worst-case timing guarantees required by safety-critical systems.

In particular, unregulated sharing of the memory hierarchy across cores can cause severe and unpredictable interference. When multiple cores concurrently access shared memory resources, their requests contend with one another, degrading application performance and undermining timing guarantees. Hardware quality-of-service (QoS) mechanisms aim to manage this contention. Partitioning these resources in space alone does not guarantee temporal isolation. Bandwidth regulation can protect latency-critical tasks from such interference, but it trades system throughput for isolation. Current solutions throttle co-running tasks far more than necessary, offering system designers a poor isolation-throughput tradeoff.

Addressing this challenge, this thesis focuses on QoS mechanisms that improve the balance between throughput and isolation. Shared memory resources such as the last-level cache (LLC) and main memory (DRAM) have parallel, banked structures, yet existing regulation treats them as monolithic. This thesis shows that contention in both arises at the bank level and proposes per-bank bandwidth regulation for the LLC and DRAM, which preserves isolation for latency-critical tasks while recovering throughput for best-effort tasks. Finally, the thesis aims to coordinate regulation across the levels of the memory hierarchy, adapting it dynamically at runtime. It will also explore matching the control mechanism to the root cause of contention, for example by controlling the number of outstanding requests, as an alternative or cooperative means to bandwidth regulation. Together, these efforts work toward a better balance between system throughput and isolation guarantees in multicore real-time systems.