Memory Bandwidth Dynamic Regulation and Throttling


Student Name: Eric Seals
Defense Date:
Location: Learned Hall, Room 3150
Chair: Heechul Yun

Alex Bardas

Drew Davidson

Abstract:

Multi-core, integrated CPU-GPU embedded systems provide new capabilities for sophisticated real-time systems with size, weight, and power limitations; however, interference between shared resources remains a challenge in providing necessary performance guarantees. The shared main memory is a notable system bottleneck - causing throughput slowdowns and timing unpredictability.

In this paper, we propose a full system mechanism which can provide memory bandwidth regulation across both CPU and the GPU complexes. This system monitors the memory controller accesses directly through hardware statistics counters, performs memory regulation at the software level for real-time CPU tasks, and incorporates a feedback-based throttling mechanism for non-critical GPU kernels using hardware within the NVIDIA Tegra X1 memory controller subsystem. The system is built as a loadable Linux kernel module that extends the MemGuard tool. We show that this system can make CPU task execution more predictable against co-running, memory intensive interference on either CPU or GPU.

Degree: MS Thesis Defense (CoE)
Degree Type: MS Thesis Defense
Degree Field: Computer Engineering