Defense Notices

Matched processing is fundamental filtering operation within radar signal processing to estimate scattering in the radar scene based on the transmit signal. Although matched processing maximizes the signal-to-noise ratio (SNR), the filtering operation is ineffective when interference is captured in the receive measurement. Adaptive interference mitigation combined with matched processing has proven to mitigate interference and estimate the radar scene. But, a known caveat of matched processing is the resulting sidelobes that may mask other scatterers. The sidelobes can be efficiently addressed by windowing but this approach also comes with limited suppression capabilities, loss in resolution, and loss in SNR. The recent emergence of mismatch processing has shown to optimally reduce sidelobes while maintaining nominal resolution and signal estimation performance. Throughout this work, re-iterative minimum-mean square error (RMMSE) adaptive and least-squares (LS) optimal mismatch processing are proposed for enhanced signal estimation in unison with adaptive interference mitigation for various radar applications including random pulse repetition interval (PRI) staggering pulse-Doppler radar, airborne ground moving target indication, and radar & communication spectrum sharing. Mismatch processing and adaptive interference cancellation each can be computationally complex for practical implementation. Sub-optimal RMMSE and LS approaches are also introduced to address computational limitations. The efficacy of these algorithms are presented using various high-fidelity Monte Carlo simulations and open-air experimental datasets. 

Quantum computing is a promising technology that can potentially demonstrate supremacy over classical computing in solving specific problems. At present, two critical challenges for quantum computing are quantum state decoherence, and low scalability of current quantum devices. Decoherence places constraints on realistic applicability of quantum algorithms as real-life applications usually require complex equivalent quantum circuits to be realized. For example, encoding classical data on quantum computers for solving I/O and data-intensive applications generally requires quantum circuits that violate decoherence constraints. In addition, current quantum devices are of small-scale having low quantum bit(qubit) counts, and often producing inaccurate or noisy measurements, which also impacts the realistic applicability of real-world quantum algorithms. Consequently, benchmarking of existing quantum algorithms and investigation of new applications are heavily dependent on classical simulations that use costly, resource-intensive computing platforms. Hardware-based emulation has been alternatively proposed as a more cost-effective and power-efficient approach. This work proposes a hardware-based emulation methodology for quantum algorithms, using cost-effective Field-Programmable Gate-Array(FPGA) technology. The proposed methodology consists of three components that are required for complete emulation of quantum algorithms; the first component models classical-to-quantum(C2Q) data encoding, the second emulates the behavior of quantum algorithms, and the third models the process of measuring the quantum state and extracting classical information, i.e., quantum-to-classical(Q2C) data decoding. The proposed emulation methodology is used to investigate and optimize methods for C2Q/Q2C data encoding/decoding, as well as several important quantum algorithms such as Quantum Fourier Transform(QFT), Quantum Haar Transform(QHT), and Quantum Grover’s Search(QGS). This work delivers contributions in terms of reducing complexities of quantum circuits, extending and optimizing quantum algorithms, and developing new quantum applications. For higher emulation performance and scalability of the framework, hardware design techniques and hardware architectural optimizations are investigated and proposed. The emulation architectures are designed and implemented on a high-performance-reconfigurable-computer(HPRC), and proposed quantum circuits are implemented on a state-of-the-art quantum processor. Experimental results show that the proposed hardware architectures enable emulation of quantum algorithms with higher scalability, higher accuracy, and higher throughput, compared to existing hardware-based emulators. As a case study, quantum image processing using multi-spectral images is considered for the experimental evaluations.