Chenyun Pan

Assistant Professor
Primary office:
785-864-6640
2030 Eaton
University of Kansas
1520 W. 15th Street
Lawrence, KS 66045


Summary

Chenyun Pan received a B.S. in microelectronics from Shanghai Jiao Tong University (Shanghai, China) in 2010 and M.S. and Ph.D. in the School of Electrical and Computer Engineering (ECE)  at Georgia Institute of Technology in 2013 and 2015, respectively. In the summer of 2014 and spring of 2015, he was a researcher at IMEC in Leuven, Belgium, focusing on emerging graphene interconnects and deeply scaled vertical FETs. From 2015 to 2018, he was a Research Scientist in the School of ECE at the Georgia Institute of Technology.

Dr. Pan’s research interest covers the modeling and optimization of energy-efficient Boolean and non-Boolean computing systems using various emerging beyond-CMOS devices, interconnects, and memory technologies. The applications include high-performance low-power circuits for deep learning applications, non-volatile in-memory computing system, and hardware security circuits. He has published more than 30 peer-reviewed IEEE journal and conference papers. He is the recipient of two Best Paper awards in the IEEE International Symposium on Quality Electronic Design and IEEE Conference on IC Design and Technology, and 2018 Research Spotlight Award in the School of ECE at Georgia Tech.

GRA positions available. Self-motivated students who are interested in pursuing research in the following areas are encouraged to contact me by email: chenyun@ku.edu

Primary Research Interests

  • Beyond-CMOS Nanoelectronic Devices and Interconnects Exploration
  • Neuromorphic Circuit Design for Deep Learning Applications
  • Nonvolatile Memory Design
  • VLSI System Design
  • Hardware Security

Teaching

University of Kansas:

EECS645 - Computer Architecture

EECS786 - Digital VLSI

Georgia Institute of Technology:

ECE3710 - Circuits and Electronics

Selected Publications

Google Scholar Webpage

Journal Publications:

Patent:

  • C. Pan, S. Dutta, and A. Naeemi, “Magnetoelectric Computational Device,” U.S. Patent 15/654,278, filed on July 19, 2017.

Conference Publications:

  • V. Huang, C. Pan and A. Naeemi, “Generic System-Level Modeling and Optimization for Beyond CMOS Device Applications,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2018.
  • C. Pan and A. Naeemi, “Beyond-CMOS Non-Boolean Logic Benchmarking: Insights and Future Directions,” Design Automation and Test in Europe (DATE), March, 2017.
  • J. Mohseni, C. Pan and A. Naeemi, “Performance Modeling and Optimization for On-Chip Interconnects in Cross-Bar ReRAM Memory Arrays,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October, 2016.
  • D. Prasad, C. Pan and A. Naeemi, “Interconnect design and optimization for advanced technology nodes,” Proceedings of SRC TECHCON, September, 2016. (Best in Session Award) 
  • S. Dutta, R. M. Iraei, C. Pan, D. Nikonov, S. Manipatruni, I. A. Young, and A. Naeemi, “Impact of Spintronics Transducers on the Performance of Spin Wave Logic Circuit,” IEEE International Conference on Nanotechnology (NANO), August, 2016.
  • C. Pan and A. Naeemi, “Beyond-CMOS Device and Interconnect Technology Benchmarking based on a Fast Cross-Layer Optimization Methodology,” Electrochemical Society (ECS) Transaction, May, 2016. (Invited Paper)
  • C. Pan, S. Chang, and A. Naeemi, “Performance Analyses and Benchmarking for Spintronic Devices and Interconnects,” IEEE International Interconnect Technology Conference (IITC), May, 2016.
  • J. Mohseni, C. Pan and A. Naeemi, “Performance Modeling and Optimization for On-Chip Interconnects in STT-MRAM Memory Arrays,” IEEE International Interconnect Technology Conference (IITC), May, 2016. (Top 5 Student Papers)
  • D. Prasad, C. Pan and A. Naeemi, “Impact of Interconnect Variability on Circuit Performance in Advanced Technology Nodes,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2016. (Best Paper Nomination)
  • J. Mohseni, C. Pan and A. Naeemi, “Performance Modeling and Optimization for On-Chip Interconnects in 2D and 3D Memory Arrays,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2016.
  • V. Huang, C. Pan and A. Naeemi, “Device/System Performance Modeling of Stacked Lateral NWFET Logic,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2016.
  • J. Mohseni, C. Pan, and A. Naeemi, “Performace Modeling and Optimization for On-Chip Interconnects in Memory Arrays,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October, 2015.
  • C. Pan, P. Raghavan, F. Catthoor, Z. Tokei, and A. Naeemi, “Technology/Circuit Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10nm Technology Node,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2015. (Best Paper Nomination)
  • C. Pan and A. Naeemi, “System-Level Chip/Package Co-Design for Multi-Core Processors Implemented with Power-Gating Technique,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October, 2014.
  • Naeemi, A. Ceyhan, V. Kumar, C. Pan, R. M. Iraei, and S. Rakheja, “BEOL Scaling Limits and Next Generation Technology Prospects,” IEEE/ACM Design Automation Conference (DAC), June, 2014. (Invited Paper)
  • C. Pan and A. Naeemi, “System-level Variation Analysis for Interconnection Networks,” IEEE International Interconnect Technology Conference (IITC), May, 2014.
  • C. Pan, S. Mukhopadhyay and A. Naeemi, “An Analytical Approach to System-level Variation Analysis and Optimization for Multi-Core Processors,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2014.
  • C. Pan and A. Naeemi, “System-level Analysis for 3D Interconnection Networks,” IEEE International Interconnect Technology Conference (IITC), June, 2013.
  • C. Pan, A. Ceyhan, and A. Naeemi, “System-level Optimization and Benchmarking for InAs Nanowire Based Gate-All-Around Tunneling FETs,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2013.
  • C. Pan and A. Naeemi, “System-Level Performance Optimization and Benchmarking for On-Chip Graphene Interconnects,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October, 2012.
  • C. Pan and A. Naeemi, “System-Level Optimization and Benchmarking of Graphene pn Junction Logic System Based on Empirical CPI Model,” IEEE International Conference on IC Design and Technology (ICICDT), May, 2012. (Best Paper Award)
  • C. Pan and A. Naeemi, “Device- and System-Level Performance Modeling for Graphene P-N Junction Logic,” IEEE International Symposium on Quality Electronic Design (ISQED), March, 2012. (Best Paper Award)

Selected Work

1. Neuromorphic Computing Circuit Using Emerging Technologies 

Biologically-inspired computing platforms are highly-efficient for solving many problems, particularly in the voice, image, and video processing, by taking advantages of massive parallel low-power computing blocks. Compounded with emerging beyond-CMOS technologies, these neuromorphic circuits lead to significant improvement in computing energy efficiency. As an example, cellular neural network (CNN) is one promising type of non-Boolean computing system that can outperform the traditional digital logic computation and mitigate the physical scaling limit of the conventional CMOS technology. 

 

Spintronic Cellular Neural Network and Its Functional Demonstration for Associative Memory Applications

2. Emerging Non-Volatile Memory Design 

To replace the conventional SRAM, DRAM, and floating gate-based FLASH memory, this project aims to develop high-density high-performance stand-alone non-volatile memory that is essential for energy-efficient computing systems. A variety of emerging technologies and memory architectures are investigated, and two examples are given as follow.

  • Spintronic Memory

Fast Read and Write Spintronic SRAM Schematic, Layout, and Performance Projection

  • 3D Crossbar Memory Array

High-Density High-Performance 3D Crossbar Memory Array and Modeling

3. Hierarchical Optimization for Generic VLSI Systems 

To design next-generation high-performance low-power VLSI computing systems, this project develops a fast and efficient hierarchical optimization engine to explore various emerging beyond-CMOS technologies and system-level innovations. When developing new technology options, all critical design parameters across all levels of abstraction must be co-optimized simultaneously to maximize the overall chip throughput. A faster device does not guarantee a larger chip throughput, because the system could be limited by the leakage power, device footprint area, interconnect network, architecture, and/or memory bandwidth. The proposed optimization engine is highly efficient so that an exhaustive exploration and searching is feasible under area or power constraints. Several representative case studies are listed as follow:

 Device Optimization: Interconnect Optimization: System-Level Optimization:

A Hierarchical Optimization Engine for Generic VLSI Systems

4. Beyond-CMOS Technology Exploration for Boolean and non-Boolean Applications 

Faced with the challenges and limitations of CMOS scaling, there is a global search for beyond-CMOS device technologies that are capable of augmenting or even replacing conventional Si CMOS technology and sustaining Moore’s Law.  There is an increasing need for a uniform benchmarking methodology to capture and evaluate the latest research and development for various beyond-CMOS proposals. Such research is critical in identifying the key limiting factors for promising devices and in guiding future research directions through modification or even reinvention of proposed devices.

Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications

    

Selected Awards & Honors

  • Research Spotlight Award, School of ECE, Georgia Institute of Technology, 2018
  • Best in Session Award, Semiconductor Research Corporation (SRC) TECHCON, 2016
  • Best Paper Nomination, IEEE International Symposium on Quality Electronic Design (ISQED), 2016
  • Top 5 Student Papers, IEEE International Interconnect Technology Conference (IITC), 2016
  • Best Paper Nomination, IEEE International Symposium on Quality Electronic Design (ISQED), 2015
  • Best Student Paper Award, IEEE International Conference on IC Design and Technology (ICICDT), 2012
  • Best Paper Award, IEEE International Symposium on Quality Electronic Design (ISQED), 2012
  • Outstanding Bachelor Thesis, School of Microelectronics, Shanghai Jiao Tong University, 2010
  • 1st Prize, National Undergraduate Electronic Design Contest in China, 2009

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