Michael Cracraft, an advisory engineer at IBM, will present “Model-to-Hardware Correlation for High-Speed Channels and Channel Sensitivities" The EECS Seminar will be at 11:00 a.m. on Friday, Oct. 1, in the Apollo Room in Nichols Hall.
Shorter design cycles and reduced budgets require high-speed circuit designers to rely more and more on simulation. Hardware revisions are expensive from a budget and a time perspective. However, simulations are only as good as the information fed into them. There are questions that define every model. What is to be modeled? How is it going to be modeled? At what scale is it to be modeled? How will you verify that your simulations are correct? Time-domain and frequency-domain measurement plans may determine how the simulations are constructed, at least for model-to-hardware correlation.
When a high-speed channel is designed, the designer does not typically simulate every possible net length and path. The routing may change before the design is finished, and the process is very time consuming. More commonly, a sample net is constructed to tune the drivers and receivers. However, with reflections, crosstalk and other factors impacting the performance, it is important to identify the worst-case design and ensure design constraints are not violated.
Cracraft graduated summa cum laude with a B.S in Electrical Engineering from the Missouri University of Science and Technology in 2000. At Missouri S&T, he was granted membership in both Tau Beta Pi and Eta Kappa Nu. He was awarded a National Science Foundation Integrative Graduate Education and Research Traineeship (IGERT) fellowship while working in the Electromagnetic Compatibility (EMC) Laboratory at Missouri S&T as a graduate student. He received his M.S. in Electrical Engineering in 2002, followed by his Ph.D. in Electrical Engineering in 2007, both from Missouri S&T. He is a member of IEEE and the Electromagnetic Compatibility Society. Since 2007, he has worked in packaging and signal integrity on Power Systems and System Z for IBM