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EECS Professor Selected for Intel® Corporation Hardware Accelerator Research Program (HARP)

February 2, 2017

Hardware accelerators and coprocessors are attracting a great deal of interest, but the effort required to program heterogeneous systems has limited their impact. Current programming tools for these technologies require a great deal of domain-specific knowledge to reformulate algorithms for FPGA, partition a design between FPGA and CPU, and orchestrate data transfers between FPGA and CPU.  In addition, portability remains a challenge between different CPU+FPGA systems. Intel® Corporation has recently established the HARP to target these challenges.

El-Araby's proposal has been chosen to be part of the second round of Intel's program; HARP 2. Intel will provide El-Araby and his students with access to computer systems containing Intel microprocessors and an Altera Arria®-10 FPGA in a multi-chip package (MCP) that incorporates Intel’s Accelerator Abstraction Layer Software in order to spur research in computer architecture, operating systems, programming tools, and innovative applications for accelerator-based computing systems. An Intel Xeon+FPGA system (Broadwell + Arria10) will be made available via one of two centralized cluster installations in the US and in Germany

In this research project, El-Araby and his group will conduct research on a framework to integrate design across these varied platforms. Their primary goal is to develop an easy-to-use and productive computing environment that enables improved application portability while maintaining performance. In doing so, they propose a Reconfigurable Hardware Virtualization (RHV) framework to share the reconfigurable resources in High-Performance Reconfigurable Computers (HPRCs) among all system microprocessors and/or processor-cores.

Reconfigurable Hardware Virtualization (RHV) framework
Reconfigurable Hardware Virtualization (RHV) framework

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